The present invention relates to semiconductor devices and more particularly, to improved methods of forming damascene metallization layers by utilization of lithographic techniques.
Semiconductor manufacturers must continually improve the power and performance of semiconductor devices while keeping the device size to a minimum. In an effort to maintain a small device size, most semiconductor manufacturers reduce individual components of the device to minimal dimensions. Furthermore, manufacturers are using methods such as vertical integration of the components, to reduce the device area consumed by the components. But by packing the components in a higher and higher density, the need for higher performance interconnects arises. As the cross sectional areas of the interconnects shrinks, line resistance and current density capacity become limiting factors of total chip performance. For example, aluminum, which has commonly been used for interconnects, has problems associated with electromigration and lowered heat dissipation. Copper, which has a lower resistivity and a greater electromigration lifetime, eliminates many of the existing problems associated with using aluminum. However, there are difficulties with fabricating copper interconnects using conventional etching techniques since copper material does not lend itself well to conventional plasma etching.
A recent approach to solving the problem of interconnecting the various conductive layers involves etch and mask sequences generally known in the art as damascene techniques. The damascene technique involves forming a plurality of trenches in a layer of insulator and subsequently filling them with metal, by way of example, copper, which is then polished down to the surface of the insulator to form the desired metal pattern. In a process generally known as dual damascening, both the metal trenches as described above and the via interconnects electrically connecting the aforementioned metal pattern and various other conductive layers are typically filled substantially simultaneously.
By way of example, FIGS. 1(a), 1(b), 1(c), 1(d), 1(e), 1(f) and 1(g) illustrate a process flow for forming a metallization layer using standard damascene techniques known in the prior art. FIG. 1(a) shows a layer stack 102 having a metal one layer 104 disposed above a substrate 106. A metal one region 108 may be a line or a via or a chain of vias in metal one layer 104. Dielectric regions 110 and 112 insulate metal one region 108 from other metal lines or vias. Though it is not shown in the figures, layer stack 102 may represent a layer within a series of layers and substrate 106 may have various processing and/or device layers disposed underneath.
FIG. 1(b) shows a dielectric layer 114 deposited above metal one layer 104. Dielectric layer 114 is usually deposited using a blanket deposition method, for example, or some type of chemical vapor deposition. Dielectric layer 114 usually comprises some type of insulating material, by way of example, a low-K dielectric.
FIG. 1(c) shows a photoresist layer 116 that is formed above dielectric layer 114. Photoresist layer 116 has been patterned using a conventional photolithography process to provide an opening 118. The process flow continues with the etching into dielectric layer 114 through opening 118, extending the depth of opening 118 through dielectric layer 114 such that metal one region 108 is exposed as shown in FIG. 1(d).
FIG. 1(e) illustrates the layer stack after photoresist layer 116 has been removed, typically by an ash process. After removal of the photoresist, a metal two layer 120 is deposited into opening 118 to make contact with metal one region 108 underneath and over dielectric layer 114 as shown in FIG. 1(f). Metal two layer 120 may be deposited by a number of methods, depending on the specific metal being used. If metal two layer 120 is aluminum, chemical vapor deposition or sputtering might be used. A copper metal two layer 120 might be depositing by electroplating, sputtering or other methods such as a blanket type of deposition that is commonly used for depositing metallic materials. Prior to deposition of metal two layer 120, an optional barrier layer (not shown in the figures to simplify the illustration) may be deposited over the surface of opening 118 if necessary, for example, to prevent the diffusion of metal into the dielectric material. This barrier layer, which is generally used with copper deposition may be, by way of example, tantalum nitride.
After deposition into opening 118 and over dielectric layer 114, metal two layer 120 is planarized down to the top of the dielectric material, leaving a metal line 122 in contact with metal one region 108 as shown in FIG. 1(g). Planarizing may be achieved by chemical-mechanical polishing, among other planarization techniques. In using the chemical mechanical polishing method, there may be an polish stop layer disposed above dielectric layer 114 (not shown in the figure to simplify the discussion).
The standard damascene approach described in the above figures has been used successfully to form metallization layers of metals that are not easily etchable, such as copper. But as device scaling progresses further and the smaller metal lines come closer and closer together, regular dielectric materials can not perform their insulating functions in a satisfactory manner, thereby resulting in cross-talking and short circuits. This gives rise to a need for better insulating materials, for example, low-K dielectric materials. However, utilizing these next generation materials such as the low-K dielectric materials in standard damascene techniques poses difficult challenges, primarily in etching the low-K dielectric material and in depositing metal on the low-K dielectric layer.
Material porosity is a major issue as these next generation materials such as the low-K dielectrics have a low dielectric constant, usually about 3 or less (with the absolute lowest k being a vacuum, which is equivalent to k=1). One way the dielectric constant can be decreased is by decreasing the density of the material, which will result in materials of greater porosity. Due to the discontinuity of the material surfaces, these dielectric materials of greater porosity pose serious problems in metal deposition, and in the case of copper, deposition of a barrier layer in addition to copper. There may be difficulties in attempting to deposit a continuous barrier layer or metal layer over a bumpy or irregular surface of the dielectric layer.
Another problem is the mechanical strength of these next generation materials, which raises concerns about their ability to withstand rigorous processes such as chemical mechanical polishing. By way of example, to accomplish the chemical mechanical polishing of metal two layer 120 in FIG. 1(f) down to the top of dielectric layer 114, dielectric layer 114 must be better able to mechanically withstand the chemical mechanical polishing process than present day low-K dielectric materials are known to be. A dielectric layer made of a material that does not have the mechanical strength to withstand the chemical mechanical polishing process may result in a shifting of the trenches that define the metal lines, as well as a lack of structural integrity on the part of the dielectric layer rendering it ineffective as an insulator. Moreover, it may be difficult to maintain a flat planar level on the top surface of dielectric layer which is conducive towards metal deposition. The interaction of the dielectric layer with the chemical mechanical polishing process may result in variations in the top surface of the dielectric layer such as bowing or having helixes of copper with interlaid dielectric in between. These variations may propagate up with the creation of additional layers.
Yet another issue is the problems associated with maintaining a proper vertical profile of the openings etched in the dielectric layer. Possible undesirable effects include bowing or sloping sidewalls, residues on the bottom surface of the opening or on top of the metal one layer. Serious challenges may also arise with photoresist removal, which changes the etching chemistry, which in turn may impact the vertical profile of the openings if the dielectric material being used is sensitive to the etching chemistry. A solution currently being used is to deposit a capping oxide layer on top of the dielectric layer subsequent to deposition of the dielectric layer, but that necessitates the inconvenience of having to deposit the capping oxide layer and to etch through the capping oxide.
Therefore, there are desired improved methods that allow for the formation of metallization layers in scaled down devices while avoiding the aforementioned problems associated with shrinking device size and using advanced materials such as copper and low-K dielectrics.